1. Field of the Invention
The present invention is related to a high-voltage device structure, particularly to a high-voltage metal oxide semiconductor (HVMOS) device structure that can prevent current leakage.
2. Description of the Prior Art
HVMOS devices are MOS devices for use under high voltage. Presently, HVMOS devices have been applied in central processing unit (CPU) power supplies, power management systems, and AC/DC converters.
Please refer to FIG. 1. FIG. 1 is a plan view schematically illustrating a conventional high-voltage N-type metal oxide semiconductor (HV NMOS) structure 10. As shown in FIG. 1, an HV NMOS device 50 is formed in a P-type substrate (not shown). The HV NMOS device 50 includes a first N-doped region 12 (indicated by a cross-hatched region), a second N-doped region 14 (indicated by a cross-hatched region), a channel diffusion region 16 (indicated by a dash-dot line) connecting portions of the first N-doped region 12 and the second N-doped region 14, and a poly-silicon gate 18 covering the channel diffusion region 16.
The HV NMOS structure 10 further includes a source diffusion region 20 located in the first N-doped region 12, a drain diffusion region 22 located in the second N-doped region 14, and an isolation structure 24 located in the P-type substrate to properly isolate the source diffusion region 20, the drain diffusion region 22, and the channel diffusion region 16. The source diffusion region 20, the drain diffusion region 22, and the poly-silicon gate 18 are electrically connected with external circuits (not shown) through contact plugs 26, 28, 30, 32, and 34.
In addition, a guard ring 40 is disposed around the HVMOS device 50 to electrically isolate MOS devices. The guard ring 40 serves as a channel stop by being doped with dopants of charge opposite the source diffusion region 20 and the drain diffusion region 22. For example, in the HV NMOS device 50, the guard ring 40 is a P-doped region that is doped with boron. However, when operated at high-voltage, if the guard ring 40 contacts the source diffusion region 20 or the drain diffusion region 22 of the HV NMOS device 50, breakdown of the device may occur. In other words, if a positive voltage is provided to the drain diffusion region 22 of the HV NMOS 50, a reverse bias will be formed around the boundary of the drain diffusion region 22 and the guard ring 40, which is a PN junction. When the bias is higher than the breakdown voltage of the PN junction, the device may be damaged. Since high operation voltage is applied to the HV MOS device 50, if the breakdown voltage is not high enough, damage of the device may occur.
In order to solve the above problem, in the prior art, a space is provided between the source and drain diffusion regions 20, 22 and the guard ring, to increase the breakdown voltage and prevent the high-voltage device from breaking down. In other words, in the prior art HVMOS device 50, the channel diffusion region 16 is longer than the source diffusion region 20 and the drain diffusion region 22. In addition, spaces where the channel diffusion region 16 is longer than both the source diffusion region 20 and the drain diffusion region 22 form two spare regions 36 and 38. However, due to the ever decreasing element size in semiconductor technology, the source diffusion region 20 and the drain diffusion region 22 are so close that parasitic current may be generated in the spare regions 36 and 38, which have high gate voltages. In addition, boron segregating to an isolation strusture interface and a low boron concentration effect may cause a kink effect or other unpredictable I-V characteristic curves, or result in a snapback effect that damages the device.
Therefore, an improved HVMOS structure is needed to solve the problem of current leakage and prevent the high-voltage device from being damaged.